This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits (IC) may be formed from arrangements of one or more input/output devices, standard devices, memory devices, and/or the like. In one scenario, memory devices may include memory arrays arranged into memory cells and the associated circuitry to write data to the memory cells and read data from the memory cells. In particular, the memory cells of a memory array, such as a random access memory (RAM) array, may be organized into rows and columns. The logic latches within these individual memory cells may be used to store a data bit that is representative of a logical “1” or “0.” These memory cells may also be interconnected by word lines (WL) and pairs of complementary bit lines (BL).
Various critical lines carrying critical signals may be used to control access to the memory cells of the memory array. For example, the critical lines carrying critical signals may include word lines carrying word line signals, where the word lines run through the memory array and are used to select a row of memory cells to be accessed. In another example, the critical lines carrying critical signals may include control lines carrying control signals, where the control signals may be used to perform particular access operations on the memory cells. Such control signals may include a column select signal, a write enable signal, a precharge signal, and/or the like.
Further, when used to access particular memory cells of the array, critical line driver circuitry may be used to drive a particular critical signal on a critical line to an asserted voltage. However, as process geometries have become smaller and memory densities higher, problems have arisen in propagation of the critical signal along its corresponding critical line. In particular, the critical lines may be implemented using one or more metal layers of the IC. As such, each critical line may have a finite resistance and capacitance, causing the critical line to behave as a distributed RC element, which may slow the critical signal from rising to the asserted value driven by critical line driver circuitry.